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<a href="#nested-classes">Data Structures</a> &#124;
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen___c_ram_cmd.html">XTrafGen_CRamCmd</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command Ram word fields.  <a href="struct_x_traf_gen___c_ram_cmd.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen___p_ram_cmd.html">XTrafGen_PRamCmd</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parameter Ram word fields.  <a href="struct_x_traf_gen___p_ram_cmd.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen___cmd.html">XTrafGen_Cmd</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command structure exposed to user.  <a href="struct_x_traf_gen___cmd.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen___cmd_entry.html">XTrafGen_CmdEntry</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command Entry structure.  <a href="struct_x_traf_gen___cmd_entry.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen___config.html">XTrafGen_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The configuration structure for Traffic Generator device.  <a href="struct_x_traf_gen___config.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen___cmd_info.html">XTrafGen_CmdInfo</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command Information Structure.  <a href="struct_x_traf_gen___cmd_info.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_traf_gen.html">XTrafGen</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> driver instance data.  <a href="struct_x_traf_gen.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Macros</h2></td></tr>
<tr class="memitem:gaefe8b2fd0fb990e5cfa429c8b49b3162"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaefe8b2fd0fb990e5cfa429c8b49b3162">MAX_NUM_ENTRIES</a>&#160;&#160;&#160;256</td></tr>
<tr class="memdesc:gaefe8b2fd0fb990e5cfa429c8b49b3162"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of command entries per region.  <a href="group__trafgen__v3__2.html#gaefe8b2fd0fb990e5cfa429c8b49b3162">More...</a><br /></td></tr>
<tr class="separator:gaefe8b2fd0fb990e5cfa429c8b49b3162"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga622293b32ccc06f19e7f568ba80a2390"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga622293b32ccc06f19e7f568ba80a2390">NUM_BLOCKS</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga622293b32ccc06f19e7f568ba80a2390"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Read and write regions.  <a href="group__trafgen__v3__2.html#ga622293b32ccc06f19e7f568ba80a2390">More...</a><br /></td></tr>
<tr class="separator:ga622293b32ccc06f19e7f568ba80a2390"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a676092267b72a3e5ad91718b914ecf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga8a676092267b72a3e5ad91718b914ecf">XTG_WRITE</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga8a676092267b72a3e5ad91718b914ecf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write Direction Flag.  <a href="group__trafgen__v3__2.html#ga8a676092267b72a3e5ad91718b914ecf">More...</a><br /></td></tr>
<tr class="separator:ga8a676092267b72a3e5ad91718b914ecf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2391f0c6f6705906f85e0da3d16e3222"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga2391f0c6f6705906f85e0da3d16e3222">XTG_READ</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga2391f0c6f6705906f85e0da3d16e3222"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Direction Flag.  <a href="group__trafgen__v3__2.html#ga2391f0c6f6705906f85e0da3d16e3222">More...</a><br /></td></tr>
<tr class="separator:ga2391f0c6f6705906f85e0da3d16e3222"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga80fcb2c884f7369ddbaffc1e51bba9ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga80fcb2c884f7369ddbaffc1e51bba9ce">XTG_MODE_FULL</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga80fcb2c884f7369ddbaffc1e51bba9ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Full Mode.  <a href="group__trafgen__v3__2.html#ga80fcb2c884f7369ddbaffc1e51bba9ce">More...</a><br /></td></tr>
<tr class="separator:ga80fcb2c884f7369ddbaffc1e51bba9ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4b6bd2e6c7f45de76c7fb1241c364347"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga4b6bd2e6c7f45de76c7fb1241c364347">XTG_MODE_BASIC</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga4b6bd2e6c7f45de76c7fb1241c364347"><td class="mdescLeft">&#160;</td><td class="mdescRight">Basic Mode.  <a href="group__trafgen__v3__2.html#ga4b6bd2e6c7f45de76c7fb1241c364347">More...</a><br /></td></tr>
<tr class="separator:ga4b6bd2e6c7f45de76c7fb1241c364347"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga15499801ae618925ac45a3a55807e1d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga15499801ae618925ac45a3a55807e1d6">XTG_MODE_STATIC</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga15499801ae618925ac45a3a55807e1d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Static Mode.  <a href="group__trafgen__v3__2.html#ga15499801ae618925ac45a3a55807e1d6">More...</a><br /></td></tr>
<tr class="separator:ga15499801ae618925ac45a3a55807e1d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf22b2f8af4980fac9d5faaf3001ab0f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaf22b2f8af4980fac9d5faaf3001ab0f0">XTG_MODE_STREAMING</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gaf22b2f8af4980fac9d5faaf3001ab0f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Streaming Mode.  <a href="group__trafgen__v3__2.html#gaf22b2f8af4980fac9d5faaf3001ab0f0">More...</a><br /></td></tr>
<tr class="separator:gaf22b2f8af4980fac9d5faaf3001ab0f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d8b67e1ec714d525de17946ec19ad49"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga3d8b67e1ec714d525de17946ec19ad49">XTG_MODE_SYS_INIT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga3d8b67e1ec714d525de17946ec19ad49"><td class="mdescLeft">&#160;</td><td class="mdescRight">System Init Mode.  <a href="group__trafgen__v3__2.html#ga3d8b67e1ec714d525de17946ec19ad49">More...</a><br /></td></tr>
<tr class="separator:ga3d8b67e1ec714d525de17946ec19ad49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7480264c1d222e138bcbc5174c388dfa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga7480264c1d222e138bcbc5174c388dfa">XTG_MWIDTH_32</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga7480264c1d222e138bcbc5174c388dfa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Width - 32.  <a href="group__trafgen__v3__2.html#ga7480264c1d222e138bcbc5174c388dfa">More...</a><br /></td></tr>
<tr class="separator:ga7480264c1d222e138bcbc5174c388dfa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3b8b2543e2717381d028703081f750d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga3b8b2543e2717381d028703081f750d9">XTG_MWIDTH_64</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga3b8b2543e2717381d028703081f750d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Width - 64.  <a href="group__trafgen__v3__2.html#ga3b8b2543e2717381d028703081f750d9">More...</a><br /></td></tr>
<tr class="separator:ga3b8b2543e2717381d028703081f750d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga01688e8360ce4e2f5f0b3fbb005ca32f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga01688e8360ce4e2f5f0b3fbb005ca32f">XTG_SWIDTH_32</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga01688e8360ce4e2f5f0b3fbb005ca32f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Width - 32.  <a href="group__trafgen__v3__2.html#ga01688e8360ce4e2f5f0b3fbb005ca32f">More...</a><br /></td></tr>
<tr class="separator:ga01688e8360ce4e2f5f0b3fbb005ca32f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a40084992daaaba41ea6f395153a417"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga9a40084992daaaba41ea6f395153a417">XTG_SWIDTH_64</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga9a40084992daaaba41ea6f395153a417"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Width - 64.  <a href="group__trafgen__v3__2.html#ga9a40084992daaaba41ea6f395153a417">More...</a><br /></td></tr>
<tr class="separator:ga9a40084992daaaba41ea6f395153a417"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaedc624adc68d449cdd422c2bcf824ae5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaedc624adc68d449cdd422c2bcf824ae5">XTG_PRM_RAM_BLOCK_SIZE</a>&#160;&#160;&#160;0x400</td></tr>
<tr class="memdesc:gaedc624adc68d449cdd422c2bcf824ae5"><td class="mdescLeft">&#160;</td><td class="mdescRight">PARAM Block Size (1KB)  <a href="group__trafgen__v3__2.html#gaedc624adc68d449cdd422c2bcf824ae5">More...</a><br /></td></tr>
<tr class="separator:gaedc624adc68d449cdd422c2bcf824ae5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae6768580423b3cbb32e1822433634463"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gae6768580423b3cbb32e1822433634463">XTG_CMD_RAM_BLOCK_SIZE</a>&#160;&#160;&#160;0x1000</td></tr>
<tr class="memdesc:gae6768580423b3cbb32e1822433634463"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cmd RAM Block Size (4KB)  <a href="group__trafgen__v3__2.html#gae6768580423b3cbb32e1822433634463">More...</a><br /></td></tr>
<tr class="separator:gae6768580423b3cbb32e1822433634463"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac0e4ea9cbcd6fb559351aee0f810d60b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gac0e4ea9cbcd6fb559351aee0f810d60b">XTG_EXTCMD_RAM_BLOCK_SIZE</a>&#160;&#160;&#160;0x400</td></tr>
<tr class="memdesc:gac0e4ea9cbcd6fb559351aee0f810d60b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended CMDRAM Block Size (1KB)  <a href="group__trafgen__v3__2.html#gac0e4ea9cbcd6fb559351aee0f810d60b">More...</a><br /></td></tr>
<tr class="separator:gac0e4ea9cbcd6fb559351aee0f810d60b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97756bfb1f0735200a2668e7431ebcf3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga97756bfb1f0735200a2668e7431ebcf3">XTG_PARAM_RAM_SIZE</a>&#160;&#160;&#160;0x800</td></tr>
<tr class="memdesc:ga97756bfb1f0735200a2668e7431ebcf3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parameter RAM (2KB)  <a href="group__trafgen__v3__2.html#ga97756bfb1f0735200a2668e7431ebcf3">More...</a><br /></td></tr>
<tr class="separator:ga97756bfb1f0735200a2668e7431ebcf3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga917ddd8cff98a1e520664e21bffc3b58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga917ddd8cff98a1e520664e21bffc3b58">XTG_COMMAND_RAM_SIZE</a>&#160;&#160;&#160;0x2000</td></tr>
<tr class="memdesc:ga917ddd8cff98a1e520664e21bffc3b58"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command RAM (8KB)  <a href="group__trafgen__v3__2.html#ga917ddd8cff98a1e520664e21bffc3b58">More...</a><br /></td></tr>
<tr class="separator:ga917ddd8cff98a1e520664e21bffc3b58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga255c930454b0fb1a4a1b9dbe7c704692"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga255c930454b0fb1a4a1b9dbe7c704692">XTG_MASTER_RAM_SIZE</a>&#160;&#160;&#160;0x2000</td></tr>
<tr class="memdesc:ga255c930454b0fb1a4a1b9dbe7c704692"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master RAM (8KB)  <a href="group__trafgen__v3__2.html#ga255c930454b0fb1a4a1b9dbe7c704692">More...</a><br /></td></tr>
<tr class="separator:ga255c930454b0fb1a4a1b9dbe7c704692"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d79e5e5aab48b68ee266961b89da00c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga4d79e5e5aab48b68ee266961b89da00c">XTrafGen_ReadCoreRevision</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga4d79e5e5aab48b68ee266961b89da00c"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_ReadCoreRevision reads revision of core.  <a href="group__trafgen__v3__2.html#ga4d79e5e5aab48b68ee266961b89da00c">More...</a><br /></td></tr>
<tr class="separator:ga4d79e5e5aab48b68ee266961b89da00c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1146dfb17253668f42cd6b2f679552cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga1146dfb17253668f42cd6b2f679552cc">XTrafGen_ReadIdWidth</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga1146dfb17253668f42cd6b2f679552cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_ReadIdWidth reads M_ID_WIDTH.  <a href="group__trafgen__v3__2.html#ga1146dfb17253668f42cd6b2f679552cc">More...</a><br /></td></tr>
<tr class="separator:ga1146dfb17253668f42cd6b2f679552cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf55f0066544c5ca956f2775e2927851d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaf55f0066544c5ca956f2775e2927851d">XTrafGen_StartMasterLogic</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaf55f0066544c5ca956f2775e2927851d"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_StartMasterLogic starts traffic generator master logic.  <a href="group__trafgen__v3__2.html#gaf55f0066544c5ca956f2775e2927851d">More...</a><br /></td></tr>
<tr class="separator:gaf55f0066544c5ca956f2775e2927851d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga067b6b58a33f91e8fb345224a12fd713"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga067b6b58a33f91e8fb345224a12fd713">XTrafGen_IsMasterLogicDone</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga067b6b58a33f91e8fb345224a12fd713"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_IsMasterLogicDone checks for traffic generator master logic completed bit.  <a href="group__trafgen__v3__2.html#ga067b6b58a33f91e8fb345224a12fd713">More...</a><br /></td></tr>
<tr class="separator:ga067b6b58a33f91e8fb345224a12fd713"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ae20ec6a0531e09e0723905c20bb572"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga7ae20ec6a0531e09e0723905c20bb572">XTrafGen_LoopEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga7ae20ec6a0531e09e0723905c20bb572"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_LoopEnable loops through the command set created using CMDRAM and PARAMRAM indefinitely in Advanced mode/Basic mode of ATG.  <a href="group__trafgen__v3__2.html#ga7ae20ec6a0531e09e0723905c20bb572">More...</a><br /></td></tr>
<tr class="separator:ga7ae20ec6a0531e09e0723905c20bb572"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad1d6d337106b8d03118d625159a93cf4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gad1d6d337106b8d03118d625159a93cf4">XTrafGen_LoopDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:gad1d6d337106b8d03118d625159a93cf4"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_LoopDisable Disbales the loop bit in Master control regiset in Advanced mode/Basic mode of ATG.  <a href="group__trafgen__v3__2.html#gad1d6d337106b8d03118d625159a93cf4">More...</a><br /></td></tr>
<tr class="separator:gad1d6d337106b8d03118d625159a93cf4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga46f61a2e9582be8d787633db33637947"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga46f61a2e9582be8d787633db33637947">XTrafGen_WriteSlaveControlReg</a>(InstancePtr,  Value)</td></tr>
<tr class="memdesc:ga46f61a2e9582be8d787633db33637947"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_WriteSlaveControlReg enables control bits of Slave Control Register.  <a href="group__trafgen__v3__2.html#ga46f61a2e9582be8d787633db33637947">More...</a><br /></td></tr>
<tr class="separator:ga46f61a2e9582be8d787633db33637947"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e86bf806f4ae36b671eef5f97b0b822"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga1e86bf806f4ae36b671eef5f97b0b822">XTrafGen_CheckforMasterComplete</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga1e86bf806f4ae36b671eef5f97b0b822"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_CheckforMasterComplete checks for master complete.  <a href="group__trafgen__v3__2.html#ga1e86bf806f4ae36b671eef5f97b0b822">More...</a><br /></td></tr>
<tr class="separator:ga1e86bf806f4ae36b671eef5f97b0b822"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga20e311a5ca0e3aa3cce768d48a2bfb88"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga20e311a5ca0e3aa3cce768d48a2bfb88">XTrafGen_ReadErrors</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga20e311a5ca0e3aa3cce768d48a2bfb88"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_ReadErrors read master and slave errors.  <a href="group__trafgen__v3__2.html#ga20e311a5ca0e3aa3cce768d48a2bfb88">More...</a><br /></td></tr>
<tr class="separator:ga20e311a5ca0e3aa3cce768d48a2bfb88"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga11a588bff0d2c58310d48da4c24126a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga11a588bff0d2c58310d48da4c24126a1">XTrafGen_EnableMasterCmpInterrupt</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga11a588bff0d2c58310d48da4c24126a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_EnableMasterCmpInterrupt enables Master logic complete bit.  <a href="group__trafgen__v3__2.html#ga11a588bff0d2c58310d48da4c24126a1">More...</a><br /></td></tr>
<tr class="separator:ga11a588bff0d2c58310d48da4c24126a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb9dd3596754f92d6c3dc73c957e812f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gadb9dd3596754f92d6c3dc73c957e812f">XTrafGen_ClearMasterCmpInterrupt</a>(InstancePtr)</td></tr>
<tr class="memdesc:gadb9dd3596754f92d6c3dc73c957e812f"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_ClearMasterCmpInterrupt clear Master logic complete interrupt bit.  <a href="group__trafgen__v3__2.html#gadb9dd3596754f92d6c3dc73c957e812f">More...</a><br /></td></tr>
<tr class="separator:gadb9dd3596754f92d6c3dc73c957e812f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1c90008bc5f3e300bd90f5ce1496793"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gae1c90008bc5f3e300bd90f5ce1496793">XTrafGen_ClearErrors</a>(InstancePtr,  Mask)</td></tr>
<tr class="memdesc:gae1c90008bc5f3e300bd90f5ce1496793"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_ClearErrors clear errors specified in <em>Mask</em>.  <a href="group__trafgen__v3__2.html#gae1c90008bc5f3e300bd90f5ce1496793">More...</a><br /></td></tr>
<tr class="separator:gae1c90008bc5f3e300bd90f5ce1496793"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e6159d969c5f451f429b9d8ec4a42f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga6e6159d969c5f451f429b9d8ec4a42f8">XTrafGen_EnableErrors</a>(InstancePtr,  Mask)</td></tr>
<tr class="memdesc:ga6e6159d969c5f451f429b9d8ec4a42f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_EnableErrors enable errors specified in <em>Mask</em>.  <a href="group__trafgen__v3__2.html#ga6e6159d969c5f451f429b9d8ec4a42f8">More...</a><br /></td></tr>
<tr class="separator:ga6e6159d969c5f451f429b9d8ec4a42f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a8a195712d5963fa07799d59045e86f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga0a8a195712d5963fa07799d59045e86f">XTrafGen_MasterErrIntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga0a8a195712d5963fa07799d59045e86f"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_MasterErrIntrEnable enables Global Master error bit.  <a href="group__trafgen__v3__2.html#ga0a8a195712d5963fa07799d59045e86f">More...</a><br /></td></tr>
<tr class="separator:ga0a8a195712d5963fa07799d59045e86f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga074810dd1b55de907889bc81a9f40579"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga074810dd1b55de907889bc81a9f40579">XTrafGen_MasterErrIntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga074810dd1b55de907889bc81a9f40579"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_MasterErrIntrDisable disables Global Master error bit.  <a href="group__trafgen__v3__2.html#ga074810dd1b55de907889bc81a9f40579">More...</a><br /></td></tr>
<tr class="separator:ga074810dd1b55de907889bc81a9f40579"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacd4a2d138602873e0614886c7e11b751"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gacd4a2d138602873e0614886c7e11b751">XTrafGen_SlaveErrIntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:gacd4a2d138602873e0614886c7e11b751"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_SlaveErrIntrEnable enables Global Slave error bit.  <a href="group__trafgen__v3__2.html#gacd4a2d138602873e0614886c7e11b751">More...</a><br /></td></tr>
<tr class="separator:gacd4a2d138602873e0614886c7e11b751"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa4b8bcf25ed401a3debc9665db06dfef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaa4b8bcf25ed401a3debc9665db06dfef">XTrafGen_SlaveErrIntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaa4b8bcf25ed401a3debc9665db06dfef"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_SlaveErrIntrDisable disables Global Slave error bit.  <a href="group__trafgen__v3__2.html#gaa4b8bcf25ed401a3debc9665db06dfef">More...</a><br /></td></tr>
<tr class="separator:gaa4b8bcf25ed401a3debc9665db06dfef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3e380d38654114c2e47162193c31febc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga3e380d38654114c2e47162193c31febc">XTrafGen_ReadConfigStatus</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga3e380d38654114c2e47162193c31febc"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_ReadConfigStatus reads Config status register.  <a href="group__trafgen__v3__2.html#ga3e380d38654114c2e47162193c31febc">More...</a><br /></td></tr>
<tr class="separator:ga3e380d38654114c2e47162193c31febc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga21218c919ca08e948a557334a8f1ba95"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga21218c919ca08e948a557334a8f1ba95">XTrafGen_StaticEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga21218c919ca08e948a557334a8f1ba95"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_StaticEnable enable the traffic genration when the core is configured Static Mode.  <a href="group__trafgen__v3__2.html#ga21218c919ca08e948a557334a8f1ba95">More...</a><br /></td></tr>
<tr class="separator:ga21218c919ca08e948a557334a8f1ba95"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab54737e40a38ba5316b487a045568b11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gab54737e40a38ba5316b487a045568b11">XTrafGen_StaticDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:gab54737e40a38ba5316b487a045568b11"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_StaticDisable disables the traffic genration on the Axi TrafGen when the core is configured in Static Mode.  <a href="group__trafgen__v3__2.html#gab54737e40a38ba5316b487a045568b11">More...</a><br /></td></tr>
<tr class="separator:gab54737e40a38ba5316b487a045568b11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga37b20b8af9dbdef32b778e28b28beebb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga37b20b8af9dbdef32b778e28b28beebb">XTrafGen_StaticVersion</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga37b20b8af9dbdef32b778e28b28beebb"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_StaticVersion returns the version value for the Axi TrafGen When configured in Static Mode.  <a href="group__trafgen__v3__2.html#ga37b20b8af9dbdef32b778e28b28beebb">More...</a><br /></td></tr>
<tr class="separator:ga37b20b8af9dbdef32b778e28b28beebb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga67433007f5c7594c7595fb71e85e938f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga67433007f5c7594c7595fb71e85e938f">XTrafGen_SetStaticBurstLen</a>(InstancePtr,  Value)</td></tr>
<tr class="memdesc:ga67433007f5c7594c7595fb71e85e938f"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_SetStaticBurstLen Configures the Burst Length for AxiTrafGen In Static Mode.  <a href="group__trafgen__v3__2.html#ga67433007f5c7594c7595fb71e85e938f">More...</a><br /></td></tr>
<tr class="separator:ga67433007f5c7594c7595fb71e85e938f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaedebd87b7d6727d97552da64fbb16d69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaedebd87b7d6727d97552da64fbb16d69">XTrafGen_GetStaticBurstLen</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaedebd87b7d6727d97552da64fbb16d69"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_GetStaticBurstLen Gets the Burst Length for AxiTrafGen in StaticMode.  <a href="group__trafgen__v3__2.html#gaedebd87b7d6727d97552da64fbb16d69">More...</a><br /></td></tr>
<tr class="separator:gaedebd87b7d6727d97552da64fbb16d69"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7b1b98f0a7cb8a9dca62ecadbc1d6d42"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga7b1b98f0a7cb8a9dca62ecadbc1d6d42">XTrafGen_GetStaticTransferDone</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga7b1b98f0a7cb8a9dca62ecadbc1d6d42"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_GetStaticTransferDone gets the state of Transfer done bit in Control register When the TraficGen is configured in Static Mode.  <a href="group__trafgen__v3__2.html#ga7b1b98f0a7cb8a9dca62ecadbc1d6d42">More...</a><br /></td></tr>
<tr class="separator:ga7b1b98f0a7cb8a9dca62ecadbc1d6d42"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa581daf24fc19f7057cd3d62baf28cf8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaa581daf24fc19f7057cd3d62baf28cf8">XTrafGen_SetStaticTransferDone</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaa581daf24fc19f7057cd3d62baf28cf8"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_SetStaticTransferDone sets the Transfer done bit in Control register When AxiTrafGen is Configured in Static Mode.  <a href="group__trafgen__v3__2.html#gaa581daf24fc19f7057cd3d62baf28cf8">More...</a><br /></td></tr>
<tr class="separator:gaa581daf24fc19f7057cd3d62baf28cf8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga865f2e2498c2c50c43b5f9c1abfc54e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga865f2e2498c2c50c43b5f9c1abfc54e2">XTrafGen_IsStaticTransferDone</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga865f2e2498c2c50c43b5f9c1abfc54e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_IsStaticTransferDone checks for reset value When Static Traffic genration Completed by reading Control Register.  <a href="group__trafgen__v3__2.html#ga865f2e2498c2c50c43b5f9c1abfc54e2">More...</a><br /></td></tr>
<tr class="separator:ga865f2e2498c2c50c43b5f9c1abfc54e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaadc216c9d0077b5906e2b07029b8877a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaadc216c9d0077b5906e2b07029b8877a">XTrafGen_StreamEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaadc216c9d0077b5906e2b07029b8877a"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_StreamEnable enable the traffic genration on the Axi TrafGen When the core is configured in Streaming Mode.  <a href="group__trafgen__v3__2.html#gaadc216c9d0077b5906e2b07029b8877a">More...</a><br /></td></tr>
<tr class="separator:gaadc216c9d0077b5906e2b07029b8877a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9254cbaa150c31ba61e141e3cdc9a4c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga9254cbaa150c31ba61e141e3cdc9a4c7">XTrafGen_StreamDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga9254cbaa150c31ba61e141e3cdc9a4c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_StreamDisable Disable the traffic genration on the Axi TrafGen When core is configured in Streaming Mode.  <a href="group__trafgen__v3__2.html#ga9254cbaa150c31ba61e141e3cdc9a4c7">More...</a><br /></td></tr>
<tr class="separator:ga9254cbaa150c31ba61e141e3cdc9a4c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97bb49960ada1e396862580a5e41755e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga97bb49960ada1e396862580a5e41755e">XTrafGen_StreamVersion</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga97bb49960ada1e396862580a5e41755e"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_StreamVersion returns the version value for the Axi TrafGen When configured in Streaming Mode.  <a href="group__trafgen__v3__2.html#ga97bb49960ada1e396862580a5e41755e">More...</a><br /></td></tr>
<tr class="separator:ga97bb49960ada1e396862580a5e41755e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae7e5d3e4f6de43f247a5f52dbade8deb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gae7e5d3e4f6de43f247a5f52dbade8deb">XTrafGen_SetStreamingTransLen</a>(InstancePtr,  Value)</td></tr>
<tr class="memdesc:gae7e5d3e4f6de43f247a5f52dbade8deb"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_SetStreamingTransLen Configures the length of transaction for AxiTrafGen in Streaming Mode.  <a href="group__trafgen__v3__2.html#gae7e5d3e4f6de43f247a5f52dbade8deb">More...</a><br /></td></tr>
<tr class="separator:gae7e5d3e4f6de43f247a5f52dbade8deb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf17c0eadf5962f5dd8ba970b77dd12e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaf17c0eadf5962f5dd8ba970b77dd12e6">XTrafGen_GetStreamingTransLen</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaf17c0eadf5962f5dd8ba970b77dd12e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_GetStreamingTransLen Gets the length of transaction for AxiTrafGen in Streaming Mode.  <a href="group__trafgen__v3__2.html#gaf17c0eadf5962f5dd8ba970b77dd12e6">More...</a><br /></td></tr>
<tr class="separator:gaf17c0eadf5962f5dd8ba970b77dd12e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9628f47e6f85fc3dba9f55c4b28b2e69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga9628f47e6f85fc3dba9f55c4b28b2e69">XTrafGen_GetStreamingTransCnt</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga9628f47e6f85fc3dba9f55c4b28b2e69"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_GetStreamingTransCnt Gets the transfer count for AxiTrafGen in Streaming Mode.  <a href="group__trafgen__v3__2.html#ga9628f47e6f85fc3dba9f55c4b28b2e69">More...</a><br /></td></tr>
<tr class="separator:ga9628f47e6f85fc3dba9f55c4b28b2e69"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab0a135f1ad92788eeb768cfe26b74b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaab0a135f1ad92788eeb768cfe26b74b3">XTrafGen_SetStreamingRandomLen</a>(InstancePtr,  Value)</td></tr>
<tr class="memdesc:gaab0a135f1ad92788eeb768cfe26b74b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_SetStreamingRandomLen Configures the random transaction length for AxiTrafGen in Streaming Mode.  <a href="group__trafgen__v3__2.html#gaab0a135f1ad92788eeb768cfe26b74b3">More...</a><br /></td></tr>
<tr class="separator:gaab0a135f1ad92788eeb768cfe26b74b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga01e30039d0fef72f9bf3d51ff437d9d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga01e30039d0fef72f9bf3d51ff437d9d2">XTrafGen_GetStreamingProgDelay</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga01e30039d0fef72f9bf3d51ff437d9d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_GetStreamingProgDelay Gets the Programmable Delay for AxiTrafGen in Streaming Mode.  <a href="group__trafgen__v3__2.html#ga01e30039d0fef72f9bf3d51ff437d9d2">More...</a><br /></td></tr>
<tr class="separator:ga01e30039d0fef72f9bf3d51ff437d9d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90d0e4161092c15a1ca821f97cdd7a4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga90d0e4161092c15a1ca821f97cdd7a4b">XTrafGen_SetStreamingTransCnt</a>(InstancePtr,  Value)</td></tr>
<tr class="memdesc:ga90d0e4161092c15a1ca821f97cdd7a4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_SetStreamingTransCnt Configures the transfer count for AxiTrafGen in Streaming Mode.  <a href="group__trafgen__v3__2.html#ga90d0e4161092c15a1ca821f97cdd7a4b">More...</a><br /></td></tr>
<tr class="separator:ga90d0e4161092c15a1ca821f97cdd7a4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3beeeec32649b7df9c049a6b08daa55a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga3beeeec32649b7df9c049a6b08daa55a">XTrafGen_SetStreamingProgDelay</a>(InstancePtr,  Value)</td></tr>
<tr class="memdesc:ga3beeeec32649b7df9c049a6b08daa55a"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_SetStreamingProgDelay Configures the Programmable Delay for AxiTrafGen in Streaming Mode.  <a href="group__trafgen__v3__2.html#ga3beeeec32649b7df9c049a6b08daa55a">More...</a><br /></td></tr>
<tr class="separator:ga3beeeec32649b7df9c049a6b08daa55a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae5372945bcdfa008f7daf48f97edbd7f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gae5372945bcdfa008f7daf48f97edbd7f">XTrafGen_SetStreamingTdestPort</a>(InstancePtr,  Value)</td></tr>
<tr class="memdesc:gae5372945bcdfa008f7daf48f97edbd7f"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_SetStreamingTdestPort Configures the Value to drive on TDEST port for Axi TrafGen in Streaming Mode.  <a href="group__trafgen__v3__2.html#gae5372945bcdfa008f7daf48f97edbd7f">More...</a><br /></td></tr>
<tr class="separator:gae5372945bcdfa008f7daf48f97edbd7f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab626edcc0e22fa88764d3cabe973a469"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gab626edcc0e22fa88764d3cabe973a469">XTrafGen_SetStreamingTransferDone</a>(InstancePtr)</td></tr>
<tr class="memdesc:gab626edcc0e22fa88764d3cabe973a469"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_SetTransferDone sets the Transfer done bit in Control register When AxiTrafGen is Configured in Streaming Mode.  <a href="group__trafgen__v3__2.html#gab626edcc0e22fa88764d3cabe973a469">More...</a><br /></td></tr>
<tr class="separator:gab626edcc0e22fa88764d3cabe973a469"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ff0fea3c2324dbd0c6edc5efd5ba709"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga0ff0fea3c2324dbd0c6edc5efd5ba709">XTrafGen_IsStreamingTransferDone</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga0ff0fea3c2324dbd0c6edc5efd5ba709"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_IsStreamingTransferDone checks for reset value When Streaming Traffic genration is Completed by reading Stream Control Register.  <a href="group__trafgen__v3__2.html#ga0ff0fea3c2324dbd0c6edc5efd5ba709">More...</a><br /></td></tr>
<tr class="separator:ga0ff0fea3c2324dbd0c6edc5efd5ba709"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5481f14f30231fcf80dafa2b77f6e8a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga5481f14f30231fcf80dafa2b77f6e8a3">XTrafGen_ResetStreamingRandomLen</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga5481f14f30231fcf80dafa2b77f6e8a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_ResetStreamingRandomLen resets the random transaction length for AxiTrafGen in Streaming Mode.  <a href="group__trafgen__v3__2.html#ga5481f14f30231fcf80dafa2b77f6e8a3">More...</a><br /></td></tr>
<tr class="separator:ga5481f14f30231fcf80dafa2b77f6e8a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:ga9000b8a48f4981622f182d63c93984cd"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen___c_ram_cmd.html">XTrafGen_CRamCmd</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga9000b8a48f4981622f182d63c93984cd">XTrafGen_CRamCmd</a></td></tr>
<tr class="memdesc:ga9000b8a48f4981622f182d63c93984cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command Ram word fields.  <a href="group__trafgen__v3__2.html#ga9000b8a48f4981622f182d63c93984cd">More...</a><br /></td></tr>
<tr class="separator:ga9000b8a48f4981622f182d63c93984cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10db2410ee506abab9d3d70f7168dde9"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen___p_ram_cmd.html">XTrafGen_PRamCmd</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga10db2410ee506abab9d3d70f7168dde9">XTrafGen_PRamCmd</a></td></tr>
<tr class="memdesc:ga10db2410ee506abab9d3d70f7168dde9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parameter Ram word fields.  <a href="group__trafgen__v3__2.html#ga10db2410ee506abab9d3d70f7168dde9">More...</a><br /></td></tr>
<tr class="separator:ga10db2410ee506abab9d3d70f7168dde9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga94123d18434c2c1ac774e8f65370f7dd"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen___cmd.html">XTrafGen_Cmd</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga94123d18434c2c1ac774e8f65370f7dd">XTrafGen_Cmd</a></td></tr>
<tr class="memdesc:ga94123d18434c2c1ac774e8f65370f7dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command structure exposed to user.  <a href="group__trafgen__v3__2.html#ga94123d18434c2c1ac774e8f65370f7dd">More...</a><br /></td></tr>
<tr class="separator:ga94123d18434c2c1ac774e8f65370f7dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga470be5d4f63cbe0f7fb87b11a7683fc1"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen___cmd_entry.html">XTrafGen_CmdEntry</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga470be5d4f63cbe0f7fb87b11a7683fc1">XTrafGen_CmdEntry</a></td></tr>
<tr class="memdesc:ga470be5d4f63cbe0f7fb87b11a7683fc1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command Entry structure.  <a href="group__trafgen__v3__2.html#ga470be5d4f63cbe0f7fb87b11a7683fc1">More...</a><br /></td></tr>
<tr class="separator:ga470be5d4f63cbe0f7fb87b11a7683fc1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ba0ed4084853050ccea879abe7c8a19"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen___config.html">XTrafGen_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga0ba0ed4084853050ccea879abe7c8a19">XTrafGen_Config</a></td></tr>
<tr class="memdesc:ga0ba0ed4084853050ccea879abe7c8a19"><td class="mdescLeft">&#160;</td><td class="mdescRight">The configuration structure for Traffic Generator device.  <a href="group__trafgen__v3__2.html#ga0ba0ed4084853050ccea879abe7c8a19">More...</a><br /></td></tr>
<tr class="separator:ga0ba0ed4084853050ccea879abe7c8a19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc2346365e8d4e0e606633d4f5eda16a"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen___cmd_info.html">XTrafGen_CmdInfo</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gabc2346365e8d4e0e606633d4f5eda16a">XTrafGen_CmdInfo</a></td></tr>
<tr class="memdesc:gabc2346365e8d4e0e606633d4f5eda16a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command Information Structure.  <a href="group__trafgen__v3__2.html#gabc2346365e8d4e0e606633d4f5eda16a">More...</a><br /></td></tr>
<tr class="separator:gabc2346365e8d4e0e606633d4f5eda16a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e9571461b3c74299c15293343a21900"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_traf_gen.html">XTrafGen</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga1e9571461b3c74299c15293343a21900">XTrafGen</a></td></tr>
<tr class="memdesc:ga1e9571461b3c74299c15293343a21900"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_traf_gen.html" title="The XTrafGen driver instance data. ">XTrafGen</a> driver instance data.  <a href="group__trafgen__v3__2.html#ga1e9571461b3c74299c15293343a21900">More...</a><br /></td></tr>
<tr class="separator:ga1e9571461b3c74299c15293343a21900"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga4d40f6d5551836dab49e0d22e8d5e1eb"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr, <a class="el" href="struct_x_traf_gen___config.html">XTrafGen_Config</a> *Config, UINTPTR EffectiveAddress)</td></tr>
<tr class="memdesc:ga4d40f6d5551836dab49e0d22e8d5e1eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initializes a AXI Traffic Generator device.  <a href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">More...</a><br /></td></tr>
<tr class="separator:ga4d40f6d5551836dab49e0d22e8d5e1eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacbf906e378777e17e7d68729315993ec"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_traf_gen___config.html">XTrafGen_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gacbf906e378777e17e7d68729315993ec">XTrafGen_LookupConfig</a> (u32 DeviceId)</td></tr>
<tr class="memdesc:gacbf906e378777e17e7d68729315993ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Look up the hardware configuration for a device instance.  <a href="group__trafgen__v3__2.html#gacbf906e378777e17e7d68729315993ec">More...</a><br /></td></tr>
<tr class="separator:gacbf906e378777e17e7d68729315993ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39eaea669c1ff2df58e54c002b43f854"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga39eaea669c1ff2df58e54c002b43f854">XTrafGen_AddCommand</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr, <a class="el" href="struct_x_traf_gen___cmd.html">XTrafGen_Cmd</a> *CmdPtr)</td></tr>
<tr class="memdesc:ga39eaea669c1ff2df58e54c002b43f854"><td class="mdescLeft">&#160;</td><td class="mdescRight">Add a command to the software list of commands.  <a href="group__trafgen__v3__2.html#ga39eaea669c1ff2df58e54c002b43f854">More...</a><br /></td></tr>
<tr class="separator:ga39eaea669c1ff2df58e54c002b43f854"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga262d850cbfc5b0495fbc2d84334a1fba"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga262d850cbfc5b0495fbc2d84334a1fba">XTrafGen_GetLastValidIndex</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr, u32 RdWrFlag)</td></tr>
<tr class="memdesc:ga262d850cbfc5b0495fbc2d84334a1fba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get last Valid Command Index of Write/Read region.  <a href="group__trafgen__v3__2.html#ga262d850cbfc5b0495fbc2d84334a1fba">More...</a><br /></td></tr>
<tr class="separator:ga262d850cbfc5b0495fbc2d84334a1fba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga14377a8884e99ce01c0c76128c939c49"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga14377a8884e99ce01c0c76128c939c49">XTrafGen_WriteCmdsToHw</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga14377a8884e99ce01c0c76128c939c49"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write Commands to internal Command and Parameter RAMs.  <a href="group__trafgen__v3__2.html#ga14377a8884e99ce01c0c76128c939c49">More...</a><br /></td></tr>
<tr class="separator:ga14377a8884e99ce01c0c76128c939c49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaea625b89454268bbbe7f93e309141c4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaaea625b89454268bbbe7f93e309141c4">XTrafGen_AccessMasterRam</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr, u32 Offset, int Length, u8 RdWrFlag, u32 *Data)</td></tr>
<tr class="memdesc:gaaea625b89454268bbbe7f93e309141c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write or Read Master RAM.  <a href="group__trafgen__v3__2.html#gaaea625b89454268bbbe7f93e309141c4">More...</a><br /></td></tr>
<tr class="separator:gaaea625b89454268bbbe7f93e309141c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad9654a81e902175a963c83edb0c37144"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gad9654a81e902175a963c83edb0c37144">XTrafGen_PrintCmds</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr)</td></tr>
<tr class="memdesc:gad9654a81e902175a963c83edb0c37144"><td class="mdescLeft">&#160;</td><td class="mdescRight">Display Command Entry values.  <a href="group__trafgen__v3__2.html#gad9654a81e902175a963c83edb0c37144">More...</a><br /></td></tr>
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<tr class="memitem:ga539d4976ad3ace9e15d993e2b18143a0"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga539d4976ad3ace9e15d993e2b18143a0">XTrafGen_EraseAllCommands</a> (<a class="el" href="struct_x_traf_gen.html">XTrafGen</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga539d4976ad3ace9e15d993e2b18143a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Erase all Command Entry values.  <a href="group__trafgen__v3__2.html#ga539d4976ad3ace9e15d993e2b18143a0">More...</a><br /></td></tr>
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